1. Technical Field
The present invention relates to a method for use in a multiprocessor, multi-node computer system which utilizes distributed memory located in various nodes when such nodes are interconnected through a communications pathway such as a crossbar device which keeps track of data transaction identifiers. The disclosure relates to a method of allocating hardware resources in a computer system by distributing the responsibility of allocating these resources across various components in the system to improve processing speed and reduce system latency.
2. Description of the Related Art
In the past, multiprocessor computer systems utilizing groups of coordinated processing systems and distributed system resources have used hardware devices to communicate between groups of processors in a single system. Such computer systems frequently group one or more microprocessor systems along with memory, input/output controllers and other devices which are local to such processors acting as a single subsystem. Such processor subsystems are frequently coupled together through hardware devices acting as communications pathways, sometimes referred to as crossbars, which allow communications between the groups of processors allowing access to each group's memory by other groups of processors.
In such systems, it is necessary to provide information through the communications pathway so that other groups of processors may know the availability of resources available to it remotely in other nodes of the system. The related art demonstrates various methods used at controlling access to resources allocating “credit based flow control” throughout a distributed system.
U.S. Pat. No. 5,630,134 issued to Haga finds a central control apparatus which provides exclusive control to processors over specific memory locations within a shared memory region. Haga is directed at controlling access to certain memory spaces and does not anticipate management of hardware resources where such resources managed are not memory regions themselves but rather resources needed to access any arbitrary memory location. The Haga disclosure does not teach management of the resources needed to access memory contents across the system.
U.S. Pat. No. 5,027,271 issued to Curley, et al., teaches the use of an apparatus which addresses partitioning and management of system resources such as storage, terminals, and memory. The Curley patent teaches the use of system resources that are controlled and managed by the operating system software, as opposed to a method for use of hardware to allocate memory resources for use across the system.
U.S. Pat. No. 4,980,822 issued to Brantley, Jr., et al., discloses a multiprocessing system having nodes containing processors and associated memory modules with dynamically allocated storage across the entire system. The Brantley disclosure teaches a method whereby the virtual memory page table entries are constructed in such a way as to assign the location of such pages of global memory that are to be used by the processor at hand as local pages of memory. The patent also teaches a method which allows interleaving sequential accesses. The present invention does not provide for manipulating page tables to achieve the method provided.
U.S. Pat. No. 5,161,227 issued to Dias, et al., discloses a multiprocessor computer system which defines a method for optimizing exclusive control of specific memory locations shared as synchronization flags in the system. In this patent, memory locations managed by the invention are identified by software and a locking mechanism is specifically invoked with software intervention. The present invention does not require software intervention and does not utilize the method taught in Dias. Furthermore, the present invention's resource management method does not relate to memory locations, but rather to resources that support the access of a memory location when such resources are not visible to the operating software.
U.S. Pat. No. 5,974,456 issued to Naghshineh, et al., teaches a method for controlling the flow of input and output requests provided from multiple processors in a system to a given input/output device or input/output bus. The present invention is not limited to input/output requests within the system and is not invoked by operating system software or user programs operating on the system. Further, the method disclosed in the present invention does not affect the requested data in the system, but only the resources used to access data within the system.
U.S. Pat. No. 5,930,484 issued to Tran, et al., defines a system that uses dynamically variable width buses to process multiple requests onto a wide system bus shared by multiple processors. This patent teaches optimizing bus band width wherein the present invention defines a centralized method of allocating buffer space for the working space of an issued request within the system, and does not attempt to pack multiple data items together on a dynamically resized system bus.
U.S. Pat. No. 5,371,897 issued to Brown, et al., teaches a method of furnishing unique worldwide identifiers to an input/output subsystem so as to support configuration of the input/output devices after a fault within the system. Although Brown teaches use of node identifiers locally, the present invention does not bear on the subject of providing unique node identifiers on a global basis throughout the system.
U.S. Pat. No. 4,956,771 issued to Neustaedter, teaches a method of managing data buffers for an input/output controller device. The method in this referenced patent requires an extensive amount of software support in both the operating system and the input/output controller device to operate. The method taught in the present invention is independent of software and does not require the participation of input/output device controllers in order for the method to operate.
While management of memory resources across a distributed processing system have been addressed in various aspects by the patents set forth above and other disclosures, none have taught a method whereby one system component can be assigned the responsibility of allocating resources on a second system component when such first component is supplying the resource consuming operations. Credit based system resource management methods, as used in the past, do not provide for obtaining additional hardware resource information useful in managing and applying system resources as they apply to distributed systems throughout a multiprocessor computer system.